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APPLICATION NOTES
AVAILABLE
X24C00 128 Bit
AN4 * AN12 * AN22 * AN26 * AN32
X24C00
Serial E2PROM
16 x 8 Bit
FEATURES
DESCRIPTION
The X24C00 is a CMOS 128 bit serial E2PROM, internally organized as 16 x 8. The X24C00 features a serial interface and software protocol allowing operation on a simple two wire bus. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. The X24C00 is fabricated with Xicor's Advanced CMOS Floating Gate technology.
* * * * * * * * * *
2.7V to 5.5V Power Supply 128 Bit Serial E2PROM Low Power CMOS --Active Current Less Than 3mA --Standby Current Less Than 50A Internally Organized 16 x 8 2 Wire Serial Interface --Bidirectional Data Transfer Protocol Byte Mode Write Self Timed Write Cycle --Typical Write Cycle Time of 5ms Push/Pull Output High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years Available Packages --8-Lead MSOP --8-Lead PDIP --8-Lead SOIC
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
MSOP/DIP/SOIC
SCL
CONTROL LOGIC
COMMAND/ADDRESS REGISTER
NC NC NC VSS
1 2 3 4 X24C00
8 7 6 5
VCC NC SCL SDA
SDA
INPUT/ OUTPUT BUFFER
SHIFT REGISTER
3836 FHD F02.1
MEMORY ARRAY
3836 FHD F01
(c) Xicor, Inc. 1991, 1995, 1996 Patents Pending 3836-1.5 6/10/96 T2/C1/D0 NS
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Characteristics subject to change without notice
X24C00
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is a push/pull output and does not require the use of a pull-up resistor. PIN NAMES Symbol NC VSS VCC SDA SCL Description No Connect Ground Supply Voltage Serial Data Serial Clock
3836 PGM T01
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C00 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. A start may be issued to terminate the input of a control word or the input of data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are also inhibited while a write is in progress. Stop Condition The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is used to reset the device during a command or data input sequence and will leave the device in the standby mode. As with starts, stops are inhibited when outputting data and while a write is in progress. Write Operation The byte write operation is initiated with a start condition. The start condition is followed by an eight bit control byte which consists of a two bit write command (0,1), four address bits, and two "don't care" bits (Figure 3).
DEVICE OPERATION The X24C00 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C00 will be considered a slave in all applications.
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X24C00
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
3836 FHD F03
Figure 2. Definition of Start and Stop Conditions
SCL
SDA START CONDITION STOP CONDITION
3836 FHD F04
Figure 3. Control Byte
START
C1 C2 A3
A2
A1
A0 XX XX
3836 FHD F05
3
X24C00
After receipt of the control byte, the X24C00 will enter the write mode and await the data to be written. This data is shifted into the device on the next eight SCL clocks. Once eight clocks have been received, the data in the shift register will be written into the memory array. While the write is in progress the X24C00 will not respond to any inputs. At any time prior to clocking in the last data bit, a stop command or a new start command will terminate the operation. If a start command is given, the X24C00 will reset all counters and will prepare to clock in the next control byte. If a stop command is given, the X24C00 will reset all counters and await the next start command. At the end of the write the X24C00 will automatically reset all counters and enter the standby mode. (Figure 4). Read Operation The byte read operation is initiated with a start condition. The start condition is followed by an eight-bit control byte which consists of a two-bit read command (1,0), four address bits, and two "don't care" bits. After receipt of the control byte the X24C00 will enter the read mode and transfer data into the shift register from the array. This data is shifted out of the device on the next eight SCL clocks. At the end of the read, all counters are reset and the X24C00 will enter the standby mode. As with a write, the read operation can be interrupted by a start or stop condition while the command or address is being clocked in. While clocking data out, starts or stops cannot be generated. During the second don't care clock cycle, starts and stops are ignored. The master must free the bus prior to the end of this clock cycle to allow the X24C00 to begin outputting data (Figures 5 and 6).
Figure 4. Write Sequence
START
0
1
A3
A2
A1
A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
3836 FHD F06
Figure 5. Read Sequence
START
1
0
A3
A2
A1
A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
3836 FHD F07
Figure 6. Read Cycle Timing
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH
D7 D6
OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
SCK
6
7
8
1
SDA IN
A0
XX
XX
SDA OUT
May change from HIGH to LOW Don't Care: Changes Allowed N/A
3836 FHD F08
4
X24C00
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X24C00 ...................................... -65C to +135C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS ............................................ -1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. +70C +85C +125C
3836 PGM T02.1
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage X24C00 X24C00-3 X24C00-2.7
Limits 5V 10% 3V to 5.5V 2.7V to 5.5V
3836 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol lCC1 ICC2 ISB1 ISB2 ILI ILO VlL(1) VIH(1) VOL VOH Parameter VCC Supply Current Read VCC Supply Current Write VCC Standby Current VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Min. Max. 1 3 100 50 10 10 VCC x 0.3 VCC + 0.5 0.4 Units mA A A A A V V V V Test Conditions SCL = VCC x 0.1/VCC x 0.9 Levels @ 1MHz, SDA = Open SCL = SDA = VCC VCC = 5V 10% SCL = SDA = VCC VCC = 2.7V VIN = VSS to VCC VOUT = VSS to VCC
-1 VCC x 0.7 VCC - 0.8
IOL = 2.1mA IOH = 1mA
3841 PGM T04.3
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol CI/O(2) CIN(2) Parameter Input/Output Capacitance (SDA) Input Capacitance (SCL) Max. 8 6 Units pF pF Test Conditions VI/O = 0V VIN = 0V
3836 PGM T05.1
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
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X24C00
POWER-UP TIMING Symbol tPUR(3) tPUW(3) Parameter Power-up to Read Operation Power-up to Write Operation Max. 2 5 Units ms ms
3836 PGM T08
EQUIVALENT A.C. LOAD CIRCUIT
5V 2.16K OUTPUT 3.07K 100pF
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
3836 PGM T06.1
3836 FHD F09.2
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read & Write Cycle Limits Symbol fSCL tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH Parameter SCL Clock Frequency SCL LOW to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock LOW Period Clock HIGH Period Start Condition Setup Time Data In Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Min. 0 500 250 500 500 250 0 250 1 300 250 50 Max. 1 350 Units MHz ns ns ns ns ns ns s ns s ns ns ns
3836 PGM T07.1
Note:
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
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X24C00
Bus Timing
tF SCL tSU:STA SDA IN tAA SDA OUT
3836 FHD F10
tHIGH
tLOW
tR
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
WRITE CYCLE LIMITS Symbol tWR(4) Parameter Write Cycle Time Min. Max. 5 Units ms
3836 PGM T09
Write Cycle Timing
SCL
SDA
D0 tWR START CONDTION X24C00 ADDRESS
3836 ILL F11.1
Note:
(4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C00 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start conditions.
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X24C00
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 TYP
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) REF. 0.193 (4.90) REF.
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3926 ILL F49
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X24C00
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
9
X24C00
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
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X24C00
ORDERING INFORMATION X24C00 Device X X -X VCC Range Blank = 5V 10% 3 = 3V to 5.5V 2.7 = 2.7V to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C Package M = 8-Lead MSOP P = 8-Lead Plastic DIP S = 8-Lead SOIC Part Mark Convention X24C00 X X Blank = 8-Lead SOIC P = 8-Lead Plastic DIP
Blank = 4.5V to 5.5V, 0C to +70C I = 4.5V to 5.5V, -40C to +85C M = 4.5V to 5.5V, -55C to +85C D = 3V to 5.5V, 0C to +70C E = 3V to 5.5V, -40C to +85C F = 2.7V to 5.5V, 0C to +70C G = 2.7V to 5.5V, -40C to +85C
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.
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